Present complementary metal oxide semiconductor (CMOS) circuits are frequently used for a variety of computer applications. Among the many uses, CMOS circuits are used in memory devices. Among memory devices, two frequently types are dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs). Unlike typical DRAMs which use internal timing signals generated from the standard row address strobe (RAS) and column address strobe (CAS) signals issued by the microprocessor, SDRAMs use internal timing signals generated from the external system clock which is the same clock the microprocessor uses. Hence, SDRAMs may operate at a much higher speed than DRAMs. U.S. Pat No. 5,386,385, issued Jan. 31, 1995, entitled "Method and Apparatus for Preventing Invalid Operating Modes and an Application To Synchronous Memory Devices", assigned to Texas Instruments Incorporated, discloses a SDRAM.
Input buffers in semiconductors act as an interface between external input signals and internal logic circuits. Input buffer designs, as disclosed in FIGS. 126, 138 and 139 of U.S. Pat No. 5,208,776, issued Mar. 02, 1993, entitled "Pulse Generation Circuit", assigned to Texas Instruments Incorporated, translate external transistor logic (TTL) voltage levels to internal logic levels. Typically, TTL levels are 0 volts for a "low" and 5 volts for a "high". Present semiconductor memories have internal operating voltages of 0 volts for a "low" and 3.3 volts for a "high"; internal operating voltages will continue to drop as operating power specifications shrink. The following United States patents, also assigned to Texas Instruments Incorporated, illustrate input buffers designs:
______________________________________ 5,612,635 Issued 03/18/97 High Noise-Margin TTL Buffer Circuit. . . 5,455,532 Issued 10/03/95 3V To 5V Receiver/Translator Using a 5V Supply. . . 5,440,248 Issued 08/08/95 Power-Saver Differential Input Buffer 5,347,184 Issued 09/13/94 Dual Receiver Edge-Triggered Digital Signal. . . 5,324,999 Issued 06/28/94 Input Buffer with Compensated Low-Pass. . . 5,291,078 Issued 03/01/94 Gate Circuits In Transition Detection Input Buffers 5,289,430 Issued 02/22/94 Self Latching Input Buffer 5,194,767 Issued 03/16/93 TTL Compatible Hysteresis Input Buffer. . . 5,034,623 Issued 07/23/91 Low Power TTL Level CMOS Input Buffer. . . ______________________________________
Referring now to prior art FIG. 1, a four stage input buffer is illustrated. The input buffer and pulse generator is illustrative of the type used in the past designs such as the 2 meg X 8 SDRAM manufactured by Texas Instruments Incorporated. Signal CLK is the external system clock, which may be, for illustrative purposes, typically around 66 megahertz. It is a LVTTL signal with logic defined at 2.0 volts and logic defined at 0.8 volts. System clocks are increasing in speed each year. Signal CKE.sub.-- is a input buffer enable signal. It operates on logic voltage levels of 0 or 3.3 volts Signal IOCLK is the output clock generated by the circuit of FIG. 1. It operates logic voltage levels of 0 or 3.3 volts.
In operation, the CLK signal and CKE.sub.-- signal are input to a NAND gate 1 (stage one) which generates a signal which is input to an invertor 2 (stage two). Ideally, the output signal IOCLK would track the external clock signal CLK. However, the external clock could have a bad duty cycle; ie., one in which the high time and low time would not be equal. It could have a long high time and a short low time or vice versa. Prior art FIGS. 2a and 2b illustrate various "bad" CLK signals of varying pulse width with FIG. 2a illustrating a long high time and FIG. 2b illustrating a short high time. Internally, the SDRAM clock IOCLK needs to be constant, as illustrated in FIG. 2c, regardless of the duty cycle of the external clock. To accomplish this, the output of invertor 2 is fed into a pulse generator forming stages 3 and 4 of the prior art FIG. 1 circuit. The pulse generator includes a delay stage and a NAND gate 3 and an invertor 4. As is known by those of ordinary skill in the art, the "speed path" of the prior art circuit of FIG. 1 is thus NAND gate 1, invertor 2, NAND gate 3 and invertor 4. The pulse generator triggers off of the rising edge of CLK and generates a rising pulse every time CLK rises. The goal is to track the rising edge of the input system CLK and have a consistent pulse width IOCLK regardless of the falling edge of the input system clock signal.
A problem, however, with the four stage approach is that a propagation delay exist which is associated with each stage. Because of the propagation delay, the rising edge of IOCLK will not occur simultaneously with CLK; an unfortunate time lag exists as illustrated in prior art FIG. 2c. The time lag affects two critical parameters of the SDRAM known as access time and hold time. Access time is the amount of time it takes to access data in the memory array. A shorter access time is desirable. Hold time affects the other inputs to the SDRAM, such as addresses and control signals, which are latched by the rising edge of IOCLK. These signals must be held by the user a certain amount time after the rising edge of IOCLK to make sure they are properly received or caught. The quicker the rising edge of IOCLK is generated, the sooner the hold time may begin. If the time before beginning hold time is shortened, more margin is added to the overall specification. Currently, the hold time specification is around 1 nanosecond and is very difficult to meet; a lot of manufactured SDRAMs fail the test and manufacturing yield is lost.
It is accordingly an object of the invention to reduce the access time in memory devices.
It also an object of the invention to reduce the time before beginning the hold time.
Other objects and advantages of the invention will be apparent to those of ordinary side in the art having reference to the following specification and drawings.